Digital microphone assembly with improved frequency response and noise characteristics

ABSTRACT

A microphone assembly includes an acoustic filter with a first highpass cut-off frequency. The microphone assembly additionally includes a forward signal path and a feedback signal path. The forward signal path is configured to amplify or buffer an electrical signal generated by a transducer in response to sound and to convert the electrical signal to a digital signal. The feedback signal path is configured to generate a digital control signal based on the digital signal and to generate and output a sequence of variable current pulses based on the digital control signal. The variable current pulses suppress frequencies of the electrical signal below a second highpass cut-off frequency, higher than the first highpass cut-off frequency.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/216,928, filed Jul. 22, 2016, the entire contents of which areincorporated herein by reference.

BACKGROUND

The following description is provided to assist the understanding of thereader. None of the information provided or references cited is admittedto be prior art.

Portable communication and computing devices such as smartphones, mobilephones, tablets etc. are compact devices which are powered fromrechargeable battery sources. The compact dimensions and battery sourceput severe constraints on the maximum acceptable dimensions and powerconsumption of microphone assemblies and microphone amplificationcircuitry utilized in such portable communication devices.

There exists a continued need to improve the sound quality androbustness of microphone assemblies, for example by improving thefrequency response accuracy and reducing noise, for example expressed asan A-weighted equivalent noise sound pressure, of the microphoneassembly. There are numerous advantages associated with an improvedaccuracy of the frequency response of the microphone assembly, forexample in connection with beamforming microphone array systems, whichmay include two, three or more individual microphone assemblies. Theimproved accuracy of the frequency response of individual microphoneassemblies leads to a predictable and stable directional response of thebeamforming microphone array system.

SUMMARY

A first aspect relates to a microphone assembly including an acousticfilter with a first highpass cut-off frequency. The microphone assemblyadditionally includes a housing having a sound port, a capacitivetransducer disposed in the housing, a forward signal path, and afeedback signal path. The forward signal path includes an amplifierhaving an input coupled to the transducer and configured to amplify orbuffer an electrical signal generated by the transducer in response tosound. The forward signal path additionally includes ananalog-to-digital converter (ADC) coupled to an output of the amplifierand configured to convert the electrical signal to a digital signalafter amplification or buffering. The feedback signal path includes apulse modulator having an input coupled to the forward signal path andconfigured to generate a digital control signal based on the digitalsignal. The feedback signal path additionally includes a currentconverter having an input coupled to an output of the pulse modulatorand an output coupled to the transducer. The current converter isconfigured to generate and output a sequence of variable current pulsesbased on the digital control signal. The variable current pulsessuppress frequencies of the electrical signal below a second highpasscut-off frequency, higher than the first highpass cut-off frequency.

A second aspect relates to an integrated circuit. The integrated circuitis connectable to a capacitive transducer disposed in a housing of amicrophone assembly. The microphone assembly includes an acoustic filterwith a first highpass cut-off frequency formed by a vent between frontand back volumes of the housing. The integrated circuit includes aforward signal path and a feedback signal path. The forward signal pathincludes an amplifier configured to amplify or buffer an electricalsignal generated by the transducer when the transducer is coupled to aninput of the amplifier. The forward signal path additionally includes ananalog-to-digital converter (ADC) coupled to an output of the amplifierand configured to convert the electrical signal to a digital signalafter amplification or buffering. The feedback signal path includes apulse modulator having an input coupled to the forward signal path andconfigured to generate a digital control signal based on the digitalsignal. The feedback signal path additionally includes a currentconverter having an input coupled to an output of the pulse modulatorand configured to generate a sequence of variable current pulses basedon the digital control signal. The output of the current modulator iscoupled to an electrode of the transducer and the transducer is coupledto the input of the amplifier. The variable current pulses suppressfrequencies of the electrical signal below a second highpass cut-offfrequency, before the electrical signal is applied to the input of theamplifier.

A third aspect relates to a method of operating a microphone assemblyhaving an acoustic filter with a first highpass cut-off frequency. Themethod includes a) converting sound into an electrical signal with acapacitive transducer disposed in a housing of the microphone assembly,b) converting the electrical signal to a digital signal with anelectrical circuit disposed in the housing, c) generating a sequence ofvariable current pulses based on a digital control signal generatedbased on the digital signal, and d) suppressing frequencies of theelectrical signal below a second highpass cutoff frequency, higher thanthe first highpass cutoff frequency and before the electrical signal isapplied to the electrical circuit, by applying the variable currentpulses to an electrode of the capacitive transducer.

The foregoing summary is illustrative only and is not intended to be inany way limiting. In addition to the illustrative aspects, embodiments,and features described above, further aspects, embodiments, and featureswill become apparent by reference to the following drawings and thedetailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features of the present disclosure will becomemore fully apparent from the following description and appended claims,taken in conjunction with the accompanying drawings. Understanding thatthese drawings depict only several embodiments in accordance with thedisclosure and are, therefore, not to be considered limiting of itsscope, the disclosure will be described with additional specificity anddetail through use of the accompanying drawings. Various embodiments aredescribed in more detail below in connection with the appended drawings,in which:

FIG. 1A shows an exemplary miniature microphone assembly in accordancewith various implementations,

FIG. 1B shows a measured A-weighted signal-to-noise ratio as function ofa highpass cut-off frequency of an acoustic transducer element of theexemplary miniature microphone assembly in accordance with variousimplementations,

FIG. 2 shows a simplified electrical block diagram of a processingcircuit of the miniature microphone assembly in accordance with variousimplementations,

FIG. 3 shows a block diagram of a digital loop filter of a feedback loopor path in accordance with various implementations;

FIG. 4 is a simplified block diagram of a hybrid Pulse-Width andPulse-Amplitude Modulator (PWAM) of the feedback loop or path of theprocessing circuit in accordance with various implementations,

FIG. 5 shows a simplified block diagram of a noise-shaping up-samplerand quantizer in accordance with various implementations;

FIG. 6 shows a schematic block diagram of the operation of a modulatorportion of the hybrid Pulse-Width and Pulse-Amplitude Modulator (PWAM)in accordance with various implementations;

FIG. 7 shows a simplified schematic block diagram of a current outputconverter forming part of a current mode DAC of the processing circuitin accordance with various implementations;

FIG. 8 is a simplified schematic block diagram of a controllable currentgenerator of the exemplary current output converter in an idle state inaccordance with various implementations;

FIGS. 9A and 9B are simplified schematic block diagrams of thecontrollable current generator operating in first and second states,respectively, in accordance with various implementations; and

FIG. 10 is a simplified schematic block diagram of an exemplarymicrophone preamplifier of the processing circuit in accordance withvarious implementations.

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof. In the drawings,similar symbols typically identify similar components, unless contextdictates otherwise. The illustrative embodiments described in thedetailed description, drawings, and claims are not meant to be limiting.Other embodiments may be utilized, and other changes may be made,without departing from the spirit or scope of the subject matterpresented here. It will be readily understood that the aspects of thepresent disclosure, as generally described herein, and illustrated inthe figures, can be arranged, substituted, combined, and designed in awide variety of different configurations, all of which are explicitlycontemplated and make part of this disclosure.

DETAILED DESCRIPTION

In the following, various exemplary embodiments of the presentmicrophone assemblies are described with reference to the appendeddrawings. The skilled person will understand that the accompanyingdrawings are schematic and simplified for clarity and therefore merelyshow details which are essential to the understanding of the presentdisclosure, while other details have been left out. Like referencenumerals refer to like elements or components throughout. Like elementsor components will therefore not necessarily be described in detail withrespect to each figure. It will further be appreciated that certainactions and/or steps may be described or depicted in a particular orderof occurrence while those skilled in the art will understand that suchspecificity with respect to sequence is not actually required.

One aspect of the present disclosure relates to a microphone assemblyincluding an acoustic transducer element configured to convert soundinto a microphone signal in accordance with a transducer frequencyresponse including a first highpass cut-off frequency. The microphoneassembly additionally includes a processing circuit including a signalamplification path configured to receive, sample and digitize themicrophone signal to provide a digital microphone signal. A frequencyresponse of the signal amplification path includes a second highpasscut-off frequency which is higher than the first highpass cut-offfrequency of the acoustic transducer element.

The transducer element may include a capacitive transducer element, e.g.a microelectromechanical system (MEMS) transducer configured to convertincoming sound into a corresponding microphone signal. The capacitivetransducer element may for example exhibit a transducer capacitancebetween 0.5 pF and 10 pF. Some embodiments of the capacitive transducerelement may include first and second mutually charged transducer plates,e.g. a diaphragm and back plate, respectively, supplying the microphonesignal. The charge may be injected onto one of the diaphragm and backplate by an appropriate high-impedance DC bias voltage supply. Theprocessing circuit may include a semiconductor die, for example amixed-signal CMOS semiconductor device integrating the preamplifier,analog-to-digital converter, digital loop filter, digital to-analogconverter and optionally various other analog and digital circuits asdiscussed below.

The microphone assembly may be shaped and sized to fit into portableaudio and communication devices such as headsets, smartphones, tabletsand mobile phones etc. The transducer element may be responsive toaudible sound.

The first highpass cut-off frequency of the acoustic transducer elementmay be determined or set by dimensions of a ventilation hole, aventilation aperture or ventilation structure of the acoustic transducerelement. This ventilation hole is also known as a static pressureequalization hole or vent. The ventilation hole acoustically connects afrontal side and a back side of a diaphragm of the acoustic transducerelement. The ventilation hole, aperture or structure may protrudethrough the diaphragm or may be located in alternative structures of theacoustic transducer element, such as a support structure of thediaphragm or backplate, as long as the frontal side and a back side ofthe diaphragm are acoustically connected. The dimensions of theventilation hole, aperture or structure may be selected such that thehighpass cut-off frequency of the acoustic transducer element is lowerthan 20 Hz, or lower than 10 Hz, such as below 5 Hz. One exemplaryembodiment includes a microelectromechanical system (MEMS) condensertransducer element with a highpass cut-off frequency of approximately 5Hz achieved by a circular ventilation hole with a diameter between 5 μmand 10 μm, such as approximately 7.5 μm. The second highpass cut-offfrequency, which is set by the signal amplification path, may be higherthan 20 Hz, 40 Hz, 100 Hz and/or 4000 Hz, for example between 100 Hz and1 kHz. In one embodiment, the second highpass cut-off frequency is atleast two octaves higher than the first highpass cut-off frequency, forexample one decade higher. The highpass cut-off frequency of the signalamplification path may be set by various types of amplification, bufferor processing circuits of the signal amplification path as discussed inadditional detail below with reference to the appended drawings.

The setting of the second highpass cut-off frequency ensures that alow-frequency response, e.g. between 20 Hz and 500 Hz, of the microphoneassembly is dominated by the second highpass cut-off frequency insteadof the first highpass cut-off frequency. The first highpass cut-offfrequency may be sufficiently low to essentially render the frequencyresponse of the microphone assembly essentially unaffected throughoutthe audio frequency range, e.g. above 20 Hz.

According to one embodiment of the microphone assembly, the signalamplification path includes a forward signal path including a summingnode for combining the microphone signal and an analog feedback signal.The signal amplification path additionally includes a feedback signalpath including a digital loop filter configured to receive and filterthe digital microphone signal and in response generate a lowpassfiltered digital feedback signal in accordance with a lowpass transferfunction of the digital loop filter; and a digital to-analog converter(DAC) configured to convert the lowpass filtered digital feedback signalinto the analog feedback signal.

The summing node may be arranged at the transducer output, for exampledirectly connected to one or two charged plates of the acoustictransducer, leading to numerous advantageous properties as discussed inadditional detail below with reference to the appended drawings.

The forward signal amplification path may include a microphonepreamplifier including an input connected to the summing node forreceipt of the microphone signal, where the microphone preamplifier isconfigured to generate at least one of an amplified microphone signaland a buffered microphone signal. The forward signal amplification pathmay additionally include an analog-to-digital converter (ADC) configuredto receive, sample and quantize the amplified or buffered microphonesignal to generate the digital microphone signal. The analog-to-digitalconverter may be adapted to produce a multibit or single-bit digitalmicrophone signal representative of the microphone signal depending onthe particular converter type. Some embodiments of the analog-to-digitalconverter may include an oversampled converter type such as a single-bitor multibit sigma-delta converter (ΣΔ) configured to generate asingle-bit (PDM) or multibit digital microphone signal at a firstsampling frequency. The multibit sigma-delta converter (ΣΔ) may beconfigured to generate the multibit digital microphone signal withsamples of two, three or four bits. The first sampling frequency may liebetween 1 MHz and 20 MHz, such as between 2.048 MHz and 4.196 MHZ, forexample 3.072 MHz. The feedback path may include a decimator arrangedin-front of an input of the digital loop filter. The decimator isconfigured for converting the single-bit (PDM) or multibit digitalmicrophone signal into a decimated multibit (PCM) microphone signal at asecond sampling frequency. The second sampling frequency is lower thanthe previously discussed first sampling frequency. The second samplingfrequency may be between 8 and 64 times lower than the first samplingfrequency, e.g. accomplished by configuring the decimator withdecimation factors between 8 and 64, such as 16 or 32. The samples ofthe decimated multibit (PCM) microphone signal may possess a highernumber of bits, e.g. between 12 and 32 bits, for example 24 bits, thanthe samples of the single-bit or multibit digital microphone signal toretain high signal resolution through the feedback path despite thereduced sampling frequency. The skilled person will understand that thepreamplifier or buffer may be integrated within the analog-to-digitalconverter in some embodiments.

The digital-to-analog converter is configured to convert the lowpassfiltered or first digital feedback signal into a corresponding analogfeedback signal which is combined with the microphone signal at thetransducer output such that a feedback loop is closed in-front of andaround the microphone preamplifier. In some embodiments, the analogfeedback signal and microphone signal may be summed by electricallyconnecting the transducer output and an output of the digital-to-analogconverter. The application of the analog feedback signal to thetransducer output of the transducer element leads to numerous advantagescompared with prior art approaches. The coupling scheme effectivelyprevents low-frequency overload of the preamplifier or buffer which mustreceive and process the full dynamic range of the microphone signalgenerated by the transducer element without unacceptable distortion.This is accomplished by an anti-phase low-frequency component suppliedby the analog feedback signal which cancels or suppresses low-frequencycomponents of the microphone signal at the input node, or nodes, of thepreamplifier or buffer. Hence, high level low-frequency components ofthe microphone signal at the input of inputs of the preamplifier orbuffer are attenuated or suppressed. The high level low-frequencycomponents of the microphone signal are caused by the exposure tointense subsonic or low-frequency sounds generated by wind noise, largemachinery etc. This suppression of high level low-frequency componentsof the microphone signal at the input or inputs of the preamplifier orbuffer markedly reduces the maximum signal level of the microphonesignal which the preamplifier or buffer must be able to handle in anundistorted manner. Hence, vulnerability of the preamplifier or bufferto low-frequency induced overload and distortion may be eliminated.

The preamplifier may be a DC-coupled design or an AC-coupled design. TheDC-coupled preamplifier or buffer possesses several advantageousproperties over the AC-coupled design due to the elimination of theresistors and capacitors of a traditional analog highpass filter used toset a highpass cut-off frequency of a forward microphone amplificationpath. The forward microphone amplification path or forward signal pathmay extend from the transducer output to at least the analog-to-digitalconverter output. The elimination of the resistors and capacitors of theanalog highpass filter at the preamplifier or buffer leads to smallersemiconductor die area, reduced thermal noise and much improvedflexibility in the choice of the highpass cut-off frequency of theforward microphone amplification path. Instead, the highpass cut-offfrequency of the forward microphone amplification path may be controlledor dominated by a lowpass cut-off frequency of the digital loop filteras discussed below. The frequency response of the digital loop filter,including its lowpass cut-off frequency, is inherently significantlymore accurate than the frequency response of the traditional analoghighpass filter, because resistors and capacitors of the analog highpassfilter exhibit substantial manufacturing spread and drift over time andtemperature making accurate frequency response control difficult,expensive or both.

The accurate frequency response setting of the forward microphoneamplification path afforded by the properties of the digital loop filteralso improves frequency response matching, inclusive phase matching,between individual microphone assemblies of a beamforming microphonearray. This improved response matching leads to improved, predictableand stable directional response of the beamforming microphone array.

The digital to-analog converter may exhibit a very large outputimpedance to supply the current of the analog feedback signal into aload including a high-impedance capacitive transducer element withoutcausing undesirable attenuation and/or distortion of the microphonesignal at the transducer output. In certain embodiments, the outputimpedance of the digital to-analog converter at 10 kHz may be largerthan 1 MΩ, such as larger than 10 MΩ, or 100 MΩ.

The skilled person will understand that the analog feedback signal maybe directly connected to the transducer output, e.g. at least onetransducer plate of a capacitive transducer element. In that context,directly means through an electrically conductive path without anyintervening active devices like transistors, but possibly throughpassive components like resistors, capacitors, electrical traces, wires,etc. This feature effectively prevents the above-mentioned overload anddistortion problems of the preamplifier and buffer at high levels of themicrophone signal caused by saturation and non-linearity of activeamplification elements like transistors of the preamplifier or buffercircuitry. This low-frequency cut-off frequency may in practice beaccurately controlled by a setting of the lowpass cut-off frequency ofthe digital loop filter as discussed above. The digital signalprocessing of the digital loop filter allows a very accurate and stablesetting of the frequency response of the forward microphoneamplification path, in particular in combination with the DC-coupledpreamplifier or buffer as discussed above.

The digital loop filter may include a lowpass filter possessing acut-off frequency placed at or above 10 Hz, for example at or above 50Hz, 100 Hz or 1000 Hz. The lowpass filter may include a first, second orthird order response characteristic. The skilled person will understandthat the lowpass cut-off frequency of the digital loop filter may beselected such that a desired highpass cut-off frequency of the forwardmicrophone amplification path is obtained. The latter highpass cut-offfrequency may be situated between 10 Hz and 4000 Hz, such as between 100Hz and 1 kHz, for various embodiments of the microphone assemblydepending on requirements of a specific application. The digital loopfilter may include an adjustable or programmable transfer function incertain embodiments of the processing circuit. The transfer function maybe controlled by filter configuration data which may determine thepreviously discussed cut-off frequency of the lowpass filter. The filterconfiguration data may include respective values of one or more filtercoefficients of the digital loop filter. The filter configuration datamay be received by the processing circuit via an integrated command andcontrol interface. The integrated command and control interface allowsthe microphone assembly to connect to a compatible data interface of thehost processor and thereby receive the filter configuration data fromthe host processor. The programmable transfer function of the digitalloop filter allows the microphone assembly to be tailored torequirements of a particular application in connection with, or after,manufacturing in a flexible manner and therefore serves to reduce thenumber of variants needed of the microphone assembly.

The processing circuit may include a digital processor implementing thefunctionality of the digital loop filter and/or other control functionsof the processing circuit such as state switching of the digitalto-analog converter, controlling the operation of a command and controlinterface connectable to host processor of a portable communicationdevice, e.g. a smartphone etc. The digital processor may include adigital state machine and/or a software programmable microprocessor suchas a digital signal processor (DSP).

According to some embodiments, the digital-to-analog converter (DAC)includes a hybrid Pulse-Width and Pulse-Amplitude Modulator (PWAM)configured for generating the analog feedback signal by converting thefirst digital feedback signal into a corresponding pulse-width andpulse-amplitude modulated signal at a higher sampling frequency than asampling frequency of the first digital feedback signal. The pulse-widthand pulse-amplitude modulated signal may include a sequence of variablewidth and amplitude current pulses generated by a current outputconverter representative of the samples of the first digital feedbacksignal. The current output converter may include a plurality ofindividually controllable current generators, for example between 8 and32 individually controllable current generators, connected in parallelto the DAC output. The skilled person will understand that thecapacitance of the capacitive transducer element at the transduceroutput effectively lowpass filters or smoothes the variable width andamplitude current pulses that may be supplied by the output of thehybrid Pulse-Width and Pulse-Amplitude Modulator to suppress oreliminate undesired high frequency components in the analog feedbacksignal.

In the above-mentioned current output converter each of the plurality ofindividually controllable current generators may include a first currentsource connected between a positive DC supply rail of the current outputconverter and the DAC output for sourcing a first current level to theDAC output; and a second current source connected between the DAC outputand a negative DC supply rail of the current output converter forsinking a second current level from the DAC output. The individuallycontrollable current generator may furthermore include a DC errorsuppression circuit configured for matching the first and second currentlevels. The matching or equalization of the first and second currentlevels by the operation of the DC error suppression circuit has severalnoticeable advantages for example leading to a linear I/O characteristicof the current output converter. The DC error suppression circuit alsoprevents the build-up of DC voltage components on the load which is anoticeable advantage in connection with driving capacitive transducerelements where DC off-sets or DC imbalances of the output signal at theDAC output will tend to drive a DC operating point of the capacitivetransducer element away from a target DC operating point as discussed infurther detail below with reference to the appended drawings.

The hybrid Pulse-Width and Pulse-Amplitude Modulator is capable ofgenerating the analog feedback signal with a high resolution at arelatively low conversion frequency as discussed in further detail belowwith reference to the appended drawings

Some embodiments of the hybrid Pulse-Width-Modulator andPulse-Amplitude-Modulator may include a noise-shaping quantizerconfigured to receive samples, having a first bit-width, of the firstdigital feedback signal outputted by the digital loop filter; andquantize the samples of the first digital feedback signal to generatesamples of a second digital feedback signal with a reduced bit-width.The noise-shaping quantizer may quantize samples of an incoming digitalsignal to fewer bits, i.e. samples with reduced bit-width. Thenoise-shaping quantizer may for example quantize samples of the firstdigital feedback signal, e.g. from 32 bits or 24 bits down to less than16 bits or less than 12 bits, such as 11 bits. The noise-shapingquantizer is configured to shape a spectrum of the quantization noisegenerated by the quantization process to reduce its audibility. Hence,the quantization noise may be pushed upwards in frequency above theaudible range, for example above 20 kHz. The first digital feedbacksignal may have a sampling frequency at or above 48 kHz, for exampleabove 96 kHz, such as 192 kHz or 384 kHz. The second digital feedbacksignal may subsequently be converted into the pulse-width andpulse-amplitude modulated signal as discussed in further detail belowwith reference to the appended drawings.

Further aspects of the present disclosure relate to a method of settinga frequency response of a signal amplification path of a microphoneassembly. The method includes a) converting incoming sound into acorresponding microphone signal by an acoustic transducer element,wherein the acoustic transducer element has a frequency responseincluding a first highpass cut-off frequency; b) sampling and quantizingthe microphone signal to generate a corresponding digital microphonesignal; c) lowpass filtering the digital microphone signal by a digitalloop filter to generate a first digital feedback signal; d) convertingthe first digital feedback signal into a corresponding analog feedbacksignal by a digital-to-analog converter (DAC); and e) combining theanalog feedback signal and the microphone signal to close a feedbackloop of the signal amplification path.

The methodology may further include 0 applying the analog feedbacksignal to at least one transducer plate of a capacitivemicroelectromechanical (MEMS) transducer element supplying themicrophone signal.

Further aspects of the present disclosure relate to a semiconductor dieincluding a processing circuit according to any of the above-describedembodiments thereof. The processing circuit may include a CMOSsemiconductor die. The processing circuit may be shaped and sized forintegration into a miniature microphone housing or package. Themicrophone assembly may therefore include a microphone housing enclosingand supporting the transducer element and the processing circuit. Abottom portion of the microphone housing may include a carrier board,such as a printed circuit board, onto which the processing circuit andthe transducer element are attached or fixed by a suitable bondingmechanism. The microphone housing may include a sound port or inletallowing sound passage to the transducer element as discussed in furtherdetail below with reference to the appended drawings.

Further aspects of the present disclosure relate to a portablecommunication device including a microphone assembly according to any ofthe above-described embodiments thereof. The portable communicationdevice may include an application processor, e.g. a microprocessor suchas a Digital Signal Processor. The application processor may include adata communication interface compliant with, and connected to, anexternally accessible data communication interface of the microphoneassembly. The data communication interface may include a proprietaryinterface or a standardized data interface such as one of I²C, USB,UART, SoundWire or SPI compliant data communication interfaces. Varioustypes of configuration data of the processing circuit for example forprogramming or adapting characteristics of the digital loop filter maybe transmitted from the application processor to the microphone assemblyas discussed in further detail below with reference to the appendeddrawings.

In some embodiments, the present microphone assembly may form part of aportable communication device such as a smartphone where one, two, threeor more microphone assemblies may be integrated for picking-up andprocessing various types of acoustic signals such as speech and music.In some exemplary embodiments of the present approaches, microphoneassemblies and methodologies may be tuned or adapted to different typesof applications through configurable parameters as discussed in furtherdetail below. These parameters may be loaded into suitable memory cellsof the microphone assembly on request via the configuration datadiscussed above, for example, using the previously mentioned command andcontrol interface. The latter may include a standardized datacommunication interface such as SoundWire, I2C, UART and SPI.

FIG. 1 shows an exemplary embodiment of a microphone assembly or system100. The microphone assembly 100 includes an acoustic transducer element102, e.g. a microelectromechanical system (MEMS) transducer, configuredto convert incoming sound into a corresponding microphone signal. Theacoustic transducer element 102 may include first and second mutuallycharged transducer plates, e.g. a diaphragm 105 and back plate 106,respectively, supplying the microphone signal. The acoustic transducerelement 102 exhibits capacitive characteristics due to the arrangementof the diaphragm 105 and back plate 106 with a transducer capacitancethat may lie between 0.5 pF and 10 pF. The charge may be injected ontoone of the diaphragm 105 and back plate 106 by an appropriatehigh-impedance DC bias voltage supply (not shown). The microphoneassembly 100 additionally includes a processing circuit 122 which mayinclude a semiconductor die, for example a mixed-signal CMOSsemiconductor device integrating the various analog and digital circuitsdiscussed below. The acoustic transducer element 102 is configured toconvert sound reaching the diaphragm 105 through the sound port 109 intoa corresponding microphone signal.

The processing circuit 122 is shaped and sized for mounting on asubstrate or carrier element 111 of the assembly 100, where the carrierelement likewise supports the capacitive transducer element 102. Theacoustic transducer element 102 generates the microphone signal at atransducer output (item 101 a of FIG. 2) in response to impinging sound.The transducer output 101 a may for example include a pad or terminal ofthe transducer element 102 electrically coupled to the processingcircuit 122 via one or more bonding wires 107 electricallyinterconnecting respective signal pads of the transducer element 102 andprocessing circuit 122. The skilled person will understand that theacoustic transducer element 102 and the processing circuit 122 may beintegrally formed on a single semiconductor die in other embodiments.The microphone assembly 100 includes a housing lid 103 mounted onto aperipheral edge of the substrate or carrier element 111 such that thehousing lid 103 and carrier element 111 jointly form a microphonehousing enclosing and protecting the transducer element 102 and theprocessing circuit 105 of the assembly 100. The sound inlet or soundport 109 may project through the carrier element 111, or through thehousing lid 103 in other embodiments, for conveying sound waves to thetransducer element 102. The frequency response of the acoustictransducer element 102 is governed by the acoustic characteristics ofthe transducer element 102 itself and the surrounding acoustic loadssuch as a back chamber 110 enclosed below the housing lid 103 and afront-chamber formed in-front of the backplate 106. The transducerfrequency response includes a highpass cut-off frequency determined bydimensions of a ventilation hole or aperture 113, which may also bereferred to as a pressure equalization hole. The ventilation hole oraperture 113 is acoustically connecting a frontal side and a back sideof the diaphragm 105 of the acoustic transducer element 102. Theventilation hole or aperture 113 protrudes through the diaphragmstructure 105 in the present transducer element 102, but the skilledperson will understand that the ventilation hole 113 may be located inalternative structures of the transducer element 102 such as thevertical support structure holding a peripheral section of the diaphragm105 and backplate 106, as long as the frontal side and a back side ofthe diaphragm 105 are acoustically connected. To set the highpasscut-off frequency of the transducer element 102 at 5 Hz, the ventilationhole or aperture 113 may be circular with a diameter between 5 and 10μm. The ventilation hole or aperture 113 is necessary to provide staticpressure or DC equalisation between the frontal side and back side ofthe diaphragm 105. Conventionally, the dimensions of this ventilationhole 113 have been selected such that the highpass cut-off frequency ofthe acoustic transducer element 102 at a relatively high frequency inaudio context for example at or above 100 Hz for the purpose ofattenuating or supressing high level low-frequency components of themicrophone signal. These high level low-frequency components of themicrophone signal may be caused by intense subsonic or low-frequencysounds generated by wind noise, large machinery, etc. and are generallyundesired within the signal amplification path of the processing circuit122. This is because high level low-frequency components tend to causeoverload and non-linear distortion of various types of active circuitryof the signal amplification path, e.g. a preamplifier or buffer and/oran analog-to-digital converter and deteriorating the sound quality ofthe microphone signal.

However, there are a number of pronounced drawbacks by the conventionalsetting of the highpass cut-off frequency of the acoustic transducerelement 102. One of these is that the acoustic noise of the acoustictransducer element 102 increases with increasing dimensions of theventilation hole 113 and corresponding increase of the highpass cut-offfrequency. This effect is caused by the increasing acoustical resistanceof the vent. Another disadvantage is that the low-frequency response ofthe microphone assembly 100, i.e. including the combined effects of theacoustic transducer element 102 and signal amplification path of theprocessing circuit 122, is dominated, or at least markedly influenced,by the highpass cut-off frequency of the acoustic transducer element102. However, the highpass cut-off frequency of the acoustic transducerelement 102 is generally rather inaccurate depending on variousdifficult controllable physical dimensions of the small ventilation hole113 and other acoustic variables. Consequently, the conventional settingof the highpass cut-off frequency of the acoustic transducer element 102leads to poor control over the low-frequency response of the microphoneassembly 100 and therefore prevents accurate frequency response matchingbetween individual microphone assemblies. In addition, the noise levelof the microphone assembly is higher than desirable.

The dimensions of the ventilation hole 113 of the acoustic transducerelement 102 in the present microphone assembly 100 are in someembodiments selected such that the highpass cut-off frequency of theacoustic transducer element 102 is arranged at a relatively lowfrequency, for example lower than 20 Hz or lower than 10 Hz, such as ator below 5 Hz. The low-frequency response, e.g. between 20 Hz and 500Hz, of the microphone assembly 100 is instead dominated by a highpasscut-off frequency of the signal amplification path of the processingcircuit 122. This highpass cut-off frequency of the signal amplificationpath may be set by various types of amplification, buffer or processingcircuits of the signal amplification path. The highpass cut-offfrequency of the signal amplification path may be higher than 20 Hz, 40Hz, 100 Hz and/or 4000 Hz, such as between 100 Hz and 1 kHz. In oneembodiment, the highpass cut-off frequency of the signal amplificationpath is at least two octaves higher than the highpass cut-off frequencyof the acoustic transducer element 102, for example one decade higher.Hence, the highpass cut-off frequency of the acoustic transducer element102 may be set to 3 Hz and the highpass cut-off frequency of the signalamplification path to 30 Hz or higher, such as 100 Hz.

One embodiment of the present microphone assembly 100 is particularlyeffective in eliminating the previously discussed low-frequency overloadproblems associated with the low setting of the highpass cut-offfrequency of the acoustic transducer element 102 by adding an analogfeedback signal, generated via a digital feedback path of the signalamplification path, to an output of the acoustic transducer element 102.This embodiment is discussed in further detail below with reference toFIGS. 2-10.

FIG. 1B shows a plot 150 of the measured A-weighted signal-to-noiseratio of the microphone assembly 100 as a function of the highpasscut-off frequency of the acoustic transducer element 102. It is evidentthat the A-weighted signal-to-noise ratio improves constantly withdecreasing value of the highpass cut-off frequency. The A-weightedsignal-to-noise ratio is for example improved by about 1 dB when thehighpass cut-off frequency of the acoustic transducer element 102 islowered from 100 Hz to about 3 Hz.

FIG. 2 shows a simplified electrical block diagram of an exemplaryembodiment of the processing circuit 122 of the miniature microphoneassembly 100. The processing circuit 122 includes the previouslydiscussed signal amplification path configured to receive, sample anddigitize the microphone signal to provide a digital microphone signal atan output 112 of an analog-to-digital converter 106. The signalamplification path of the present embodiment includes a forward signalpath and a feedback signal path. The forward signal path includes asumming node or junction 132 connected to the transducer output 101 afor combining the microphone signal and the analog feedback signalsupplied by a digital to-analog converter (DAC) 130. The forward signalpath additionally includes a preamplifier or buffer 104 connected to anoutput of the summing node 132 and the previously mentionedanalog-to-digital converter 106 connected to an output of thepreamplifier or buffer 104. The forward signal path may be DC-coupledfrom the transducer output 101 a to the digital microphone signal atoutput 112 for the reasons discussed in additional detail below. Thecharacteristics and functionality of the feedback signal path extendingfrom the output 112 of the analog-to-digital converter 106 to thesumming node 132 is discussed in detail below.

The preamplifier or buffer 104 of the processing circuit 122 has aninput node or terminal 101 b connected to the transducer output 101 a ofthe transducer element 102 for receipt of the microphone signal producedby the transducer element 102. The output of the preamplifier 104supplies an amplified and/or buffered microphone signal to ananalog-to-digital converter 106 which configured for receipt, samplingand quantization of the amplified or buffered microphone signal togenerate a corresponding digital microphone signal. Theanalog-to-digital converter 106 may be adapted to produce a multibit orsingle-bit digital microphone signal representative of the microphonesignal depending on the particular converter type. Some embodiments ofthe analog-to-digital converter 106 includes a sigma-delta converter(ΣΔ) configured to generate a single-bit (PDM) digital microphone signalat a first sampling frequency. The first sampling frequency may liebetween 2 MHz and 20 MHz such as 3.072 MHz. The skilled person willunderstand that the preamplifier 104 may be integrated with theanalog-to-digital converter 106 in other embodiments.

The digital microphone signal is transmitted to an input of a commandand control interface 110 configured to receive various types of datacommands and filter configuration data for a programmable digital loopfilter 120 from a host processor (not shown) of a portable communicationdevice, e.g. a smartphone. The command/control interface 110 may includea separate clock line 116 (CLK) that clocks data on a data line 118(DATA) of the interface 110. The command and control interface 110 mayinclude a standardized data communication interface according to variousserial data communication protocols, e.g. I²C, USB, UART, SoundWire orSPI. The command and control interface 110 is configured to structureand encode the digital microphone signal in accordance with the relevantprotocol of the interface 110 and transmit the digital microphone signalto the host processor. The microphone assembly 100 may be configured toreceive and utilize various types of configuration data transmitted bythe host processor. The configuration data may include data concerning aconfiguration of the processing circuit 122, such as filter coefficientsof the digital loop filter 120.

The processing circuit 122 includes a feedback path extending at leastfrom the digital microphone signal at the output 112 of theanalog-to-digital converter 106 and back to the transducer output 101 a,or microphone preamplifier input node 101 b, since these nodes areelectrically connected. The feedback path supplies an analog feedbacksignal to the summing node at the transducer output 101 a such that thepath may be operative to set a highpass cut-off frequency of thefrequency response of the forward microphone amplification path from thetransducer output to the output 112 of the analog-to-digital converter106. This highpass cut-off frequency may in practice be accuratelycontrolled by a setting of a lowpass cut-off frequency of the digitalloop filter 120 as discussed above. The digital loop filter may via itsdigital processing nature exhibit a very accurate and stable frequencyresponse setting in contrast to frequency response settings ofconventional analog filters, which rely on values of components likecapacitors and resistors to determine the frequency response. Componentslike capacitors and resistors exhibit substantial manufacturing spreadof component values and drift over time and temperature such that thefrequency response setting of conventional analog filters are lessaccurate and stable than desired.

If the analog-to-digital converter 106 produces a digital microphonesignal as a single-bit (PDM) digital microphone signal or a multibitdigital microphone signal with 2-4 bit samples, the digital feedbackloop of the processing circuit 122 may include a decimator 115 arrangedin-front of, e.g., at the input of, the digital loop filter 120. Thisdecimator 115 may be configured for converting the single-bit (PDM) ormultibit digital microphone signal into a decimated multibit (PCM)feedback signal at a second sampling frequency. The second samplingfrequency is lower than the first sampling frequency, which may liebetween 2 MHz and 20 MHz, of the single-bit (PDM) digital microphonesignal as discussed above. The second sampling frequency may be between8 and 64 times lower than the first sampling frequency, e.g.accomplished by configuring the decimator 115 with decimation factorsbetween 8 and 64, such as 16 or 32. The samples of the decimatedmultibit feedback signal may include between 16 and 32 bits to maintaina high signal resolution in the digital feedback path. This decimationand associated lowpass filtering of the single-bit (PDM) digitalmicrophone signal may be helpful to suppress high-frequency noisecomponents of the single-bit (PDM) digital microphone signal. Thedecimated multibit feedback signal is applied to an input of the digitalloop filter 120 which filters the signal in accordance with anadjustable or fixed transfer function, such as the previously discussedlowpass frequency response, of the filter 120 to in response generate afirst digital feedback signal at a filter output. Exemplary topologiesand transfer functions of the digital loop filter 120 are discussed indetail below.

The first digital feedback signal supplied by the digital loop filter120 is applied to a digital-to-analog converter (DAC) of the digitalfeedback loop. The DAC includes a hybrid Pulse-Width and Pulse-AmplitudeModulator (PWAM) 125 connected in series with a current output converter(IDAC) 130. The DAC is configured to convert the first digital feedbacksignal into a corresponding analog feedback signal which is applied tothe microphone preamplifier input node 101 b. The latter node 101 b isconnected to the transducer output 101 a as discussed before therebyclosing the digital feedback loop. The skilled person will understandthat the transducer output may be an extremely high impedance circuitnode, e.g. an impedance corresponding to a capacitance of 0.5 pF to 10pF, of a miniature capacitive transducer element. This property of thetransducer output and the design and electrical properties, inparticular output impedance, of the current output converter 130 arediscussed in further detail below with reference to the schematicdiagram of the converter 130. The application of the analog feedbacksignal to the transducer output of the miniature capacitive transducerelement 102 leads to numerous advantages compared with prior artapproaches. The direct coupling of the analog feedback signal to thetransducer output effectively prevents low-frequency overload of thepreamplifier or buffer 104 and/or the converter 106. This isaccomplished by the lowpass filtering of the analog feedback signalcarried out by the digital loop filter 120 which lowpass filteringcancels or suppresses low-frequency components of the microphone signalat the input node 101 b, or input nodes, of the preamplifier or buffer104. Furthermore, the noise floor of the microphone assembly 100 may belowered by tailoring a frequency response of the miniature capacitivetransducer element 102 to the accurate frequency response of the forwardmicrophone amplification path. Furthermore, the accurate control overthe frequency response of the forward microphone amplification pathimproves frequency response matching, inclusive phase matching, betweenindividual microphone assemblies of a beamforming microphone array whichmay include 2, 3 or more microphone assemblies. This improved responsematching leads to improved, predictable and stable directional responseof beamforming microphone array.

The upper portion of FIG. 3 shows a block diagram of an exemplaryembodiment of the previously discussed digital loop filter 120 of thedigital feedback loop or path of the processing circuit 122. The digitalloop filter 120 has second order lowpass filter characteristics using aclassical IIR filter bi-quad topology. The skilled person willunderstand that other digital filter types and topologies, such as FIRfilters or other types of IIR filter topologies, may be utilized inalternative embodiments of the digital loop filter 120. Likewise, otherfilter orders may be used. The transfer function of the illustrateddigital loop filter 120 is determined by values of the filtercoefficients which include: a1, a2, b0, b1 and b2. The frequencyresponse graph 300 of the lower portion of FIG. 3 shows an exemplarymagnitude response 310 of the digital loop filter 120 where the lowpasscut-off frequency has been tuned to about 200 Hz. The correspondingmagnitude response 305 of the forward microphone amplification path forthis particular setting of the response 310 of the digital loop filteris also plotted. The skilled person will notice the expected 2^(nd)order highpass magnitude response of the forward microphoneamplification path. The highpass cut-off frequency is set toapproximately 30 Hz. The skilled person will understand that the lowpasscut-off frequency of the digital loop filter 120 may be adjusted over abroad frequency range to obtain a desired highpass cut-off frequency ofthe forward microphone amplification path. The latter highpass cut-offfrequency may be situated in the frequency range between 10 Hz and 200Hz for various embodiments of the microphone assembly depending onrequirements of a specific application.

The skilled person will understand that certain embodiments of theprocessing circuit 122 may include an adjustable or programmabletransfer function of the digital loop filter 120 where the transferfunction is controlled by filter configuration data. The filterconfiguration data may include respective values of one or more of thepreviously discussed filter coefficients a1, a2, b0, b1 and b2. Thefilter configuration data may be received by the processing circuit 122via the previously discussed command and control interface 110 from ahost processor. The programmable transfer function of the digital loopfilter 120 allows the microphone assembly to be tailored to requirementsof a particular application after manufacturing in a flexible manner andtherefore reduces the number of variants needed of the microphoneassembly.

Other types of configuration data for various circuits and functions ofthe processing circuit 122 may likewise be programmed through thecommand and control interface 110. The configuration data, includingfilter configuration data, may be stored in rewriteable memory cells(not shown) of the processing circuit such as flash memory, EEPROM, RAM,register files or flip-flops. These rewriteable memory cells may hold orstore certain default values of the filter configuration data.

FIG. 4 shows a simplified block diagram of an exemplary embodiment ofthe previously discussed hybrid Pulse-Width and Pulse-AmplitudeModulator (PWAM) 125 of the feedback path of the processing circuit. Theoutput of the digital loop filter 120 is connected to the input of thePWAM 125 such that the previously discussed first digital feedbacksignal is applied to the input of the PWAM 125. The first digitalfeedback signal may be a multibit signal with a relatively highresolution—for example between 16 and 32 bits per sample, such as 24bits per sample, to maintain a high signal resolution through thefeedback path. The sampling frequency of the first digital feedbacksignal may lie between 32 kHz and 384 kHz for example between 96 kHz and192 kHz. The PWAM 125 includes a noise-shaping up-sampler and quantizer410 at the input receiving the first digital feedback signal. Thenoise-shaping up-sampler and quantizer 410 raises the sampling frequencyof the first digital feedback signal with a pre-set or programmableratio, for example an integer ratio between 2 and 16 to generate asecond digital feedback signal 415 at a second sampling frequency. Thenoise-shaping up-sampler and quantizer 410 is furthermore configured toquantize samples of the second digital feedback signal to a smallernumber of bits than the samples of the first digital feedback signal.According to one exemplary embodiment of the quantizer 410 the samplesof the first digital feedback signal have 24 bits per sample while thesamples of the second digital feedback signal have been decimated to 11bits. These samples may be generated according to a signed sample formatwhere a sign bit takes one bit and a magnitude portion is represented bythe residual 10 bits of the sample.

FIG. 5 shows a simplified block diagram of the noise-shaping up-samplerand quantizer 410 of the PWAM 125. The first digital feedback signal isrepresented by X(z) and the second digital feedback signal by X(z)+E(z),where E(z) represents a quantization noise component caused by thequantization operation carried out by the quantizer 504. Thenoise-shaping up-sampler and quantizer 410 includes a noise-shapingfeedback loop extending through loop filter Hn(z) 506 to a second adder510 on the input side, which adder shapes the spectrum of the generatedquantization noise to higher frequencies and therefore maintains arelatively high resolution of the second digital feedback signalthroughout the audio frequency range despite the quantization. Thenoise-shaping up-sampler and quantizer 410 may include a feedforwardloop as illustrated extending to an output side summer 512. Thenoise-shaping up-sampler and quantizer 410 may also include theillustrated Dither generator 502, which adds a pseudo-random noisesignal of appropriate level to the first digital feedback signal at theinput of the noise-shaping up-sampler and quantizer 410 using a firstinput side adder 508. This pseudo-random noise signal may reduce audibleartefacts associated with the quantization operation in a well-knownmanner.

Referring further to FIG. 4, the PWAM 125 additionally includes amodulator 420 connected to the output of the noise-shaping up-samplerand quantizer 410 for receipt of the second digital feedback signalX(z)+E(z). The operation and functionality of an exemplary embodiment ofthe modulator 420 is schematically illustrated in FIG. 6. The modulator420 takes the second feedback digital signal in the multibit (PCM)format and converts the second feedback digital signal into apulse-width and pulse-amplitude modulated signal. The sampling frequencyof this pulse-width and pulse-amplitude modulated signal may be markedlyhigher than the sampling frequency of the second digital feedback signalas discussed below. The sampling frequency of the pulse-width andpulse-amplitude modulated signal 425 may be at least 16 times higherthan the sampling frequency of the second digital feedback signal, suchas 32 or 64 times higher. One embodiment of the modulator 420 accepts a192 kHz sampling frequency of the second digital feedback signal andgenerates a corresponding pulse-width and pulse-amplitude modulatedsignal at a sampling frequency of 12.288 MHz, and hence raises thesampling frequency of the latter by an upsampling factor of 64. Thepulse-width and pulse-amplitude modulated signal 425 may be applied tothe current output converter (IDAC) 130 (see, e.g., FIG. 4). The currentoutput converter (IDAC) 130 is configured to convert or transform thepulse-width and pulse-amplitude modulated signal into a correspondingsequence of variable width and amplitude current pulses by controllinghow individually controllable current generators (illustrated in FIGS. 7and 8) are activated. The current output converter (IDAC) 130 mayinclude an appropriately configured digital state machine. Oneembodiment of the current output converter (IDAC) 130 may include adynamic element matching circuit 432 as schematically illustrated wherethe selection of individually controllable current generators of thecurrent output converter is carried out in a randomized manner toaverage out offsets between nominally identical current generators.

Referring to FIG. 6, in one embodiment, the second digital feedbacksignal X(z)+E(z) is applied to the input of the modulator 420 and thesampling frequency raised with a predetermined ratio, N, such as 64. Inthe present embodiment, the resolution of the second digital feedbacksignal is 11 bits as discussed previously. A dividing block or circuit603 divides each 11 bits sample of the second digital feedback signalwith N to compute respective modulus values and remainder values of thesamples. The drawing shows four exemplary values, 138, 40, 522 and 276using decimal notation, of the 11 bit samples of the second digitalfeedback signal expressed in decimal format initially. The decimalsample value 138 is divided by 64 producing a modulus value of 2 and aremainder value of 10 as illustrated. The corresponding computation isalso illustrated for the three remaining samples 40, 522 and 276. Thedecimal sample value 138 is converted into binary format showing how themodulus value 2 corresponds to 00010b and the remainder value of 10corresponds to 001010b. A first variable width and amplitude pulse 610of the pulse-width and pulse-amplitude modulated signal is generated byconversion of the decimal sample value 138. The first variable width andamplitude pulse 610 is essentially constructed from two segments. Afirst pulse segment (2*64) has an amplitude of “2” (y-axis scale)spanning over a full pulse width, i.e. 100% modulation and pulseamplitude of 2—hence representing the modulus value “2”. The firstvariable width and amplitude pulse 610 additionally includes a secondpulse segment (1*10) spanning over merely 10 sample time clocks of the12.288 MHz sampling frequency of the pulse-width and pulse-amplitudemodulated signal. Stated in another way, the decimal sample value 138 isconverted into an “analog” variable width and amplitude pulse with acorresponding pulse area.

The conversion of the decimal sample value 40 into the second variablewidth and amplitude pulse 620 is also illustrated. The decimal samplevalue 40 leads to a modulus value of 0 and a remainder value of 40 asillustrated. The corresponding, second, variable width and amplitudepulse 620 reflects this outcome by merely including a second pulsesegment (1*40) with a “one” amplitude and spanning over merely 40 sampletime clocks of the 12.288 MHz sampling frequency of the pulse-width andpulse-amplitude modulated signal. The conversion of the decimal samplevalue 522 into a third variable width and amplitude pulse 630 is finallyillustrated using the same principles outlined above. The skilled personwill understand that the modulator 420 is configured to convert incomingsample values into corresponding sequence of variable width andamplitude pulses where the pulse area of each of the variable width andamplitude pulses 610, 620, 630 represents the sample value in question.Hence, each of the variable width and amplitude pulses 610, 620, 630 canbe viewed as an analog representation of the sample value in question.

The skilled person will understand that the modulator 420 may beconfigured to generate the variable width and amplitude pulses followingdifferent modulation schemes. In the present embodiment, each of thevariable width and amplitude pulses is preferably centred at a midpointof the pulse period, i.e. centered, at the sample clock time 32 in thisembodiment using an upsampling factor of 64. This pulse centering isoften referred to as double-edge pulse-width modulation. However, otherembodiments of the modulator 420 may be adapted to build the variablewidth and amplitude pulses by applying single-edge modulation.

FIG. 7 shows a simplified schematic block diagram of an exemplaryembodiment of the current output converter 130 forming part of thecurrent mode DAC of the processing circuit. The current output converter130 includes a predetermined number, N, of individually controllablecurrent generators IDAC1, IDAC2, IDAC3, IDACN for example between 4 and32 current generators such as 16 current generators. The respectiveoutputs of the N individually controllable current generators areconnected in parallel to a common DAC output node 131. A capacitivetransducer element 702 is connected to the common DAC output node 131.The skilled person will understand that the capacitive transducerelement 702 may include the previously discussed capacitive transducerelement 102 of a miniature microphone assembly for sound reproduction.However, other types of capacitive transducer elements for sensing ofvarious types of physical variables may in the alternative be driven bythe present current mode DAC 702. The N individually controllablecurrent generators IDAC1, IDAC2, IDAC3, IDACN may be nominally identicalbut the skilled person will understand that component variationsassociated with semiconductor manufacturing may cause minor variationsof characteristics between the controllable current generators, inparticular current sinking and sourcing capabilities. Each of the Nindividually controllable current generators IDAC1, IDAC2, IDAC3, IDACNis configured to selectively source current into the capacitivetransducer element 702 or sink current from the capacitive transducerelement 702 in accordance with the switching control carried out by thecurrent output converter (IDAC) 130, and thereby charge or dischargevoltage across the element 702. Each of the N individually controllablecurrent generators IDAC1, IDAC2, IDAC3, IDACN can be considered aone-bit or 1.5 bit binary values +1 or −1. The sourcing and sinking ofthe predetermined current amount or level may be carried out byselecting between first state and second states of the controllablecurrent generator. Finally, each of the individually controllablecurrent generators may include a third state or an idle/zero outputstate where the current generator neither sources nor sinks currentto/from its output. In this idle state, the current generator may beplaced in a high-impedance mode effectively disconnecting the currentgenerator from the common DAC output 131 as discussed in further detailbelow. The skilled person will appreciate that the maximum positiveoutput value of the current converter may correspond to setting all Nindividually controllable current generators IDAC1, IDAC2, IDAC3, IDACNto source current while the maximum negative output value corresponds tosetting all N individually controllable current generators IDAC1, IDAC2,IDAC3, IDACN to sink current.

FIG. 8 is a simplified schematic block diagram of the controllablecurrent generator IDACN of the current output converter 130 when placedin the idle state or off-state discussed above. The controllable currentgenerator IDACN includes a first current source 802 and a second currentsource 804 connected in series between the positive DC supply rail VDDand a negative DC supply rail which is ground (GND) in the presentembodiment. A first switch pair, including switches SW2 and SW5, iscoupled in-between the first and second current sources 802, 804 and isoperating in a synchronized manner where both switches aresimultaneously closed/conducting or open/non-conducting. The switches ofthe first switch pair SW2 and SW5 are closed in the idle state while theresidual SW1, SW3, SW4 and SW6 are placed in open/non-conducting statesas illustrated. This means that the current flowing through the firstcurrent source 802 and second current source 804 runs directly from VDDto GND as illustrated by the current path 810. Consequently, each of thefirst and second current sources 802, 804 is electrically disconnectedfrom the output node 831 and the controllable current generator IDACNdoes therefore not source or sink any noticeable current to thecapacitive transducer element 702 when placed in the idle state.

The controllable current generator IDACN additionally includes a DCvoltage reference 806 connected to an inverting input of a differentialloop amplifier 808, e.g. an operational amplifier or other differentialamplifier, of a feedback regulation loop of the IDACN. The voltage ofthe DC voltage reference 806 may be equal to one-half VDD. Thedifferential loop amplifier 808 has a non-inverting input (+) connectedto a midpoint node 812 arranged in-between the first switch pair SW2,SW5. An output of the differential loop amplifier 808 is connected acontrol input 805 of the second current source 804 where the controlinput 805 is configured to adjust the current level of the secondcurrent source 804. The operation of the differential loop amplifier 808therefore seeks to dynamically or adaptively adjust the voltage at themidpoint node 812 to approximately one-half VDD, which is the voltageset at the negative input of the differential loop amplifier 808 byadjusting the current flowing through second current source 804 via thecontrol input 805. This adaptive adjustment of the voltage at themidpoint node 812 is carried out by a feedback regulation loop. Hence,the differential loop amplifier 808, the second current source 804 andthe DC voltage reference 806 therefore jointly form a DC errorsuppression circuit which is configured to match or align the first andsecond current levels supplied by the first and second current sources802, 804 during the idle state of the controllable current generatorIDACN. In certain embodiments, the differential loop amplifier 808 maypossess a relatively small bandwidth, or large time constant, comparedto the sampling frequency of the incoming pulse-width andpulse-amplitude modulated signal. The upper cut-off frequency of thedifferential loop amplifier 808 may for example be smaller than 100 kHz,or smaller than 40 kHz, which effectively performs a slow averaging ofthe current source balancing to secure a long-term zero DC offset at theoutput of each of the controllable current generators.

This property has several noticeable advantages, for example leading toa linear I/O characteristic of the current output converter 130. The DCerror suppression circuit also prevents build-up of DC voltagecomponents on the load which is a noticeable advantage in connectionwith driving capacitive transducer elements where DC off-sets or DCimbalances of the analog feedback signal will tend to drive the DCoperating point of the capacitive transducer element away from a targetDC operating point. This potential build-up of DC off-set is caused bythe charge integration carried out by the capacitance of the capacitivetransducer element. The controllable current generator IDACN isoperating in the previously discussed idle state where the output node831 is in a high-impedance state supplying substantially zero currentoutput. Each of the switches SW1, SW2, SW3, SW4, SW5 and SW6 may includea controllable semiconductor switch, for example a MOSFET. Each of theswitches SW1, SW2, SW3, SW4, SW5 and SW6 may include a control terminal,for example a gate terminal of a MOSFET, which switches the controllablesemiconductor switch between its conducting and non-conducting states.These control terminals are connected to the previously discussedcurrent output converter (IDAC) 130. The current level supplied by thefirst and second current sources 802, 804 may vary depending onrequirements of a particular application such as a load impedance, e.g.the capacitance of the capacitive transducer element 702 in the presentembodiment, the sampling frequency of the pulse-width andpulse-amplitude modulated signal, the number of parallel connectedcontrollable current generators of the current output converter 130,etc. In one exemplary embodiment of the current output converter 130including 16 controllable current generators, the respective currents ofthe first and second current sources 802, 804 are set to about 100 pA,e.g. between 50 pA and 200 pA, when configured for driving a 1-4 pFcapacitive transducer element. The current settings of the controllablecurrent generators generally depend on a dv/dt at the peak amplitude ofthe analog feedback signal at the highest frequency of interest of thefeedback loop. The currents of the controllable current generatorsshould preferably be capable of charging the capacitance of thecapacitive transducer element 102 without slew-induced distortion underthese conditions. The highest frequency of interest of the analogfeedback signal may lie between 300 Hz and 3 kHz, for example about 1kHz, in exemplary embodiments of the microphone assembly 100.

An output impedance at 10 kHz of each of the individually controllablecurrent generators IDAC1, IDAC2, IDAC3, IDACN is in some embodimentspreferably larger than 1 MΩ, such as larger than 10 MΩ or 100 MΩ, whenoperating in either the first state or the second state.

FIG. 9A is a simplified schematic block diagram of the controllablecurrent generator IDACN of the current output converter 130 when placedin the first state, or +1 state, discussed above where the output 831 issourcing the predetermined current level to the capacitive transducerelement 702 or other load circuit. In the first state, the switches ofthe first switch pair SW2 and SW5 are open or non-conducting and theswitches SW1 and SW6 are both open or non-conducting as illustrated. Theresidual switches SW4 and SW3 are in contrast placed in conducting orclosed states as illustrated. This combination of switch states meansthat the current flowing through the first current source 802 is sourcedinto the capacitive transducer element 702 via current path 810 a whilethe current generated by the second current source 804 runs from the DCvoltage reference 806, which may be equal to one-half VDD, directly toGND via the current path 810 b. Consequently, the controllable currentgenerator IDACN sources the predetermined current level to thecapacitive transducer element 702 when placed in the first state. Theskilled person will understand that the DC balancing of the currentlevels of the first current source 802 and the second current source 804is still maintained by the operation of the previously discussed DCerror suppression circuit.

FIG. 9B is a simplified schematic block diagram of the controllablecurrent generator IDACN of the current output converter 130 when placedin the second state, or −1 state, discussed above where the output 831is sinking the predetermined current level from the capacitivetransducer element 702 or other load circuit to discharge the loadcircuit. In the second state, the switches of the first switch pair SW2and SW5 are open or non-conducting and the switches SW4 and SW3 are bothopen or non-conducting as illustrated. The residual switches SW1 and SW6are in contrast placed in conducting or closed states as illustrated.This combination of switch states means that the current flowing throughthe first current source 802 is sourced into the DC voltage reference806 and thereafter to GND via the current path 880 a. In contrast, thepredetermined current generated by the second current source 804 isdrawn out of the capacitive transducer element 702 via current path 880b to discharge the capacitive transducer element 702. Consequently, thecontrollable current generator IDACN sinks the predetermined currentlevel from the capacitive transducer element 702 when placed in thesecond state. The skilled person will understand that the DC balancingof the current levels of the first current source 802 and the secondcurrent source 804 is still maintained by the operation of thepreviously discussed DC error suppression circuit.

The skilled person will understand that above outlined switcharrangement and associated switching scheme of the switches SW1, SW2,SW3, SW4, SW5 and SW6 through the first, second and third states of eachof the controllable current generators allow the first and secondcurrent sources to operate in an unswitched manner even during timeperiods where they do not source or sink current to the load circuit.Instead, the superfluous current of particular current generator isdirected through the DC voltage reference 806 by selecting anappropriate setting of the switches. This feature eliminates switchingnoise for example caused by charge injection from repetitious switchingof the first and second current sources when cycling through the first,second and third states.

FIG. 10 is a simplified schematic block diagram of an exemplaryAC-coupled microphone preamplifier 104 suitable for use in theprocessing circuit to interface to the transducer element at the inputside and to a differential input of the previously discussedanalog-to-digital converter 106 at the output side. The skilled personwill understand that other embodiments of the processing circuit mayinclude a DC-coupled preamplifier to achieve the previously discussedadvantages.

The microphone preamplifier 104 includes a unity gain buffer stage 1001coupled in series with an AC-coupled gain stage 1003. The input voltageVin to the unity gain buffer stage 1001 includes the microphone signalsupplied via the previously discussed (see, e.g., FIG. 2) input node 101b connected to the transducer output 101 a of the transducer element102. The unity gain buffer stage 1001 is single-ended in the presentembodiment and delivers a buffered microphone signal or voltage to theinput 1005 of the AC-coupled gain stage 1003. The small signal gain ofthe ac-coupled gain stage 1003 to a positive output at Vop is determinedby a capacitance ratio between capacitors C1 and C2 and may lie between12 and 30 dB. The small signal gain of the AC-coupled gain stage 1003 toa negative output at Von is determined by a capacitance ratio betweencapacitors C4 and C3. The latter small signal is preferably set equal tothe small signal gain to the positive output at Vop of the AC-coupledgain stage 1003. Consequently, the microphone preamplifier 104 generatesan amplified microphone signal in differential or balanced format acrossthe positive negative outputs Vop, Von based on the single-endedmicrophone signal at the input 101 b. The unity gain buffer stage 1001may exhibit an extremely high input impedance to avoid loading thetransducer output in view of the potentially very high output impedanceof the transducer element as discussed above. If the transducer elementincludes the previously discussed capacitive transducer element 102 theinput impedance of the unity gain buffer stage 1001 may be larger than100 MΩ such as larger than 1 GΩ.

The differential or balanced microphone voltage at the positive andnegative outputs Vop, Von is applied to a differential input of theanalog-to-digital converter for conversion into the single-bit ormultibit digital microphone signal as discussed above.

The herein described subject matter sometimes illustrates differentcomponents contained within, or connected with, different othercomponents. It is to be understood that such depicted architectures aremerely exemplary, and that in fact many other architectures can beimplemented which achieve the same functionality. In a conceptual sense,any arrangement of components to achieve the same functionality iseffectively “associated” such that the desired functionality isachieved. Hence, any two components herein combined to achieve aparticular functionality can be seen as “associated with” each othersuch that the desired functionality is achieved, irrespective ofarchitectures or intermedial components. Likewise, any two components soassociated can also be viewed as being “operably connected,” or“operably coupled,” to each other to achieve the desired functionality,and any two components capable of being so associated can also be viewedas being “operably couplable,” to each other to achieve the desiredfunctionality. Specific examples of operably couplable include but arenot limited to physically mateable and/or physically interactingcomponents and/or wirelessly interactable and/or wirelessly interactingcomponents and/or logically interacting and/or logically interactablecomponents.

With respect to the use of substantially any plural and/or singularterms herein, those having skill in the art can translate from theplural to the singular and/or from the singular to the plural as isappropriate to the context and/or application. The varioussingular/plural permutations may be expressly set forth herein for sakeof clarity.

It will be understood by those within the art that, in general, termsused herein, and especially in the appended claims (e.g., bodies of theappended claims) are generally intended as “open” terms (e.g., the term“including” should be interpreted as “including but not limited to,” theterm “having” should be interpreted as “having at least,” the term“includes” should be interpreted as “includes but is not limited to,”etc.).

It will be further understood by those within the art that if a specificnumber of an introduced claim recitation is intended, such an intentwill be explicitly recited in the claim, and in the absence of suchrecitation no such intent is present. For example, as an aid tounderstanding, the following appended claims may contain usage of theintroductory phrases “at least one” and “one or more” to introduce claimrecitations. However, the use of such phrases should not be construed toimply that the introduction of a claim recitation by the indefinitearticles “a” or “an” limits any particular claim containing suchintroduced claim recitation to inventions containing only one suchrecitation, even when the same claim includes the introductory phrases“one or more” or “at least one” and indefinite articles such as “a” or“an” (e.g., “a” and/or “an” should typically be interpreted to mean “atleast one” or “one or more”); the same holds true for the use ofdefinite articles used to introduce claim recitations. In addition, evenif a specific number of an introduced claim recitation is explicitlyrecited, those skilled in the art will recognize that such recitationshould typically be interpreted to mean at least the recited number(e.g., the bare recitation of “two recitations,” without othermodifiers, typically means at least two recitations, or two or morerecitations).

Furthermore, in those instances where a convention analogous to “atleast one of A, B, and C, etc.” is used, in general such a constructionis intended in the sense one having skill in the art would understandthe convention (e.g., “a system having at least one of A, B, and C”would include but not be limited to systems that have A alone, B alone,C alone, A and B together, A and C together, B and C together, and/or A,B, and C together, etc.). In those instances where a conventionanalogous to “at least one of A, B, or C, etc.” is used, in general sucha construction is intended in the sense one having skill in the artwould understand the convention (e.g., “a system having at least one ofA, B, or C” would include but not be limited to systems that have Aalone, B alone, C alone, A and B together, A and C together, B and Ctogether, and/or A, B, and C together, etc.). It will be furtherunderstood by those within the art that virtually any disjunctive wordand/or phrase presenting two or more alternative terms, whether in thedescription, claims, or drawings, should be understood to contemplatethe possibilities of including one of the terms, either of the terms, orboth terms. For example, the phrase “A or B” will be understood toinclude the possibilities of “A” or “B” or “A and B.” Further, unlessotherwise noted, the use of the words “approximate,” “about,” “around,”“substantially,” etc., mean plus or minus ten percent.

The foregoing description of illustrative embodiments has been presentedfor purposes of illustration and of description. It is not intended tobe exhaustive or limiting with respect to the precise form disclosed,and modifications and variations are possible in light of the aboveteachings or may be acquired from practice of the disclosed embodiments.It is intended that the scope of the invention be defined by the claimsappended hereto and their equivalents.

What is claimed is:
 1. A microphone assembly having an acoustic filterwith a first highpass cut-off frequency, the microphone assemblycomprising: a housing having a sound port; a capacitive transducerdisposed in the housing; a forward signal path comprising: an amplifierhaving an input coupled to the transducer and configured to amplify orbuffer an electrical signal generated by the transducer in response tosound; and an analog-to-digital converter (ADC) coupled to an output ofthe amplifier and configured to convert the electrical signal to adigital signal after amplification or buffering; a feedback signal pathcomprising: a pulse modulator having an input coupled to the forwardsignal path and configured to generate a digital control signal based onthe digital signal; and a current converter having an input coupled toan output of the pulse modulator and an output coupled to thetransducer, the current converter configured to generate and output asequence of variable current pulses based on the digital control signal,wherein the variable current pulses suppress frequencies of theelectrical signal below a second highpass cut-off frequency, higher thanthe first highpass cut-off frequency.
 2. The assembly of claim 1, thecurrent converter is coupled to an electrode of the transducer, whereinthe variable current pulses suppress frequencies below the secondhighpass cut-off frequency of the electrical signal before theelectrical signal is applied to the forward signal path.
 3. The assemblyof claim 2, wherein the transducer comprises a microelectromechanicalsystems (MEMS) element having a capacitance between 0.5 pF and 10 pF,and wherein the first highpass cut-off frequency is lower than 5 Hz. 4.The assembly of claim 2, wherein the digital control signal is apulse-width and pulse-amplitude modulated signal and the currentconverter is a current digital-to-analog converter (IDAC).
 5. Theassembly of claim 2, wherein the feedback signal path further comprisesa noise-shaping quantizer between the forward signal path and the pulsemodulator, the noise-shaping quantizer configured to quantize thedigital signal before generation of the digital control signal.
 6. Theassembly of claim 5, the feedback signal path includes a digital loopfilter between the forward signal path and the pulse modulator, whereinthe digital loop filter is configured to receive and low pass filter thedigital signal provided to the pulse modulator.
 7. The assembly of claim2, the feedback signal path includes a digital loop filter between theforward signal path and the pulse modulator, wherein the digital loopfilter is configured to receive and low pass filter the digital signalprovided to the pulse modulator.
 8. The assembly of claim 7, wherein thefeedback signal path comprises a decimator between the digital loopfilter and the forward signal path, the decimator configured to converta single-bit or multibit digital signal generated by the ADC into adecimated digital signal at a lower sampling frequency than thesingle-bit or multibit digital signal.
 9. The assembly of claim 7, theelectrical circuit further comprising a control interface for receipt offilter configuration data from a host device external to the microphoneassembly, wherein a lowpass transfer function of the digital loop filteris configurable by the filter configuration data.
 10. The assembly ofclaim 2, wherein the amplifier is DC-coupled to the transducer.
 11. Theassembly of claim 2, wherein the transducer includes a vent betweenfront and back volumes of the housing, and wherein the output of thecurrent converter is coupled to the electrode of the transducer withoutany intervening active devices.
 12. An integrated circuit connectable toa capacitive transducer disposed in a housing of a microphone assemblyhaving an acoustic filter with a first highpass cut-off frequency formedby a vent between front and back volumes of the housing, the integratedcircuit comprising: a forward signal path including: an amplifierconfigured to amplify or buffer an electrical signal generated by thetransducer when the transducer is coupled to an input of the amplifier;and an analog-to-digital converter (ADC) coupled to an output of theamplifier and configured to convert the electrical signal to a digitalsignal after amplification or buffering; a feedback signal pathcomprising: a pulse modulator having an input coupled to the forwardsignal path and configured to generate a digital control signal based onthe digital signal; and a current converter having an input coupled toan output of the pulse modulator and configured to generate a sequenceof variable current pulses based on the digital control signal, wherein,when the output of the current modulator is coupled to an electrode ofthe transducer and the transducer is coupled to the input of theamplifier, the variable current pulses suppress frequencies of theelectrical signal below a second highpass cut-off frequency, higher thanthe first highpass cut-off frequency, before the electrical signal isapplied to the input of the amplifier.
 13. The integrated circuit ofclaim 12, wherein the digital control signal is a pulse-width andpulse-amplitude modulated signal and the current converter is a currentdigital-to-analog converter (IDAC).
 14. The integrated circuit of claim12, wherein the feedback signal path further comprises a noise-shapingquantizer between the forward signal path and the pulse modulator, thenoise-shaping quantizer configured to quantize the digital signal beforegeneration of the digital control signal.
 15. The integrated circuit ofclaim 14, the feedback signal path includes a digital loop filterbetween the forward signal path and the pulse modulator, wherein thedigital loop filter is configured to receive and lowpass filter thedigital signal provided to the pulse modulator.
 16. The integratedcircuit of claim 12, the feedback signal path includes a digital loopfilter between the forward signal path and the pulse modulator, whereinthe digital loop filter is configured to receive and lowpass filter thedigital signal provided to the pulse modulator.
 17. The integratedcircuit of claim 16, wherein the feedback signal path comprises adecimator between the digital loop filter and the forward signal path,the decimator configured to convert a single-bit or multibit digitalsignal generated by the ADC into a decimated digital signal at a lowersampling frequency than the single-bit or multibit digital signal. 18.The integrated circuit of claim 16, the electrical circuit furthercomprising a control interface for receipt of filter configuration datafrom a host device external to the microphone assembly, wherein alowpass transfer function of the digital loop filter is adjustable bythe filter configuration data.
 19. The integrated circuit of claim 13 incombination with a capacitive transducer having first and secondspace-apart electrodes, wherein the output of the IDAC is coupled to thefirst or second electrode of the transducer without any interveningactive devices.
 20. A method of operating a microphone assembly havingan acoustic filter with a first highpass cut-off frequency, the methodcomprising: converting sound into an electrical signal with a capacitivetransducer disposed in a housing of the microphone assembly; convertingthe electrical signal to a digital signal with an electrical circuitdisposed in the housing; generating a sequence of variable currentpulses based on a digital control signal generated based on the digitalsignal; and suppressing frequencies of the electrical signal below asecond highpass cut-off frequency, higher than the first highpasscut-off frequency and before the electrical signal is applied to theelectrical circuit, by applying the variable current pulses to anelectrode of the capacitive transducer.